1. Field of the Invention
The present invention relates to the field of fabrication of integrated circuits, and, more particularly, to a method for improving the etch behavior of semiconductor device features.
2. Description of the Related Art
The fabrication of integrated circuits requires tiny features of precisely controlled shape and size, for example, a gate electrode, to be formed in a layer of material on an appropriate substrate, such as a silicon substrate. With increasing integration density of the integrated circuits, it becomes more and more crucial to reliably and reproducibly create the minimum feature size, also referred to as critical dimension (CD), within a specific layer of material. The tiny features of precisely controlled shape and size are generated by treating the layer of material by means of, for example, etching, wherein a mask layer is formed over the layer of material to define the tiny features in the layer of material. In general, a mask layer may consist of a layer of photoresist being patterned by a photolithography process.
During the photolithography process, the photoresist may be spin-coated onto the wafer substrate and subsequently selectively exposed to deep ultraviolet radiation. Bottom anti-reflective coating (BARC) layers are required to minimize reflections and corresponding stray light exposure during the photolithography process. Without a bottom anti-reflective coating layer, exposure of the highly sensitive photoresist in undesired regions might be caused by light reflected at underlying layers. Therefore, controlling the critical dimensions, i.e., the size and shape of the tiny features, may be more difficult. Thus, bottom anti-reflective coating layers are essential in the fabrication of field effect transistors in Ultra-Large-Scale-Integrated (ULSI) devices. Typically, inorganic materials, such as silicon nitride, are employed to form the bottom anti-reflective coating layer. The bottom anti-reflective coating layer may also act as an etch stop layer in the subsequent etch process, structuring the photoresist layer, the anti-reflective coating layer and the layer of material, to form the tiny regions. After the removal of the residual photoresist layer, the structured anti-reflective coating layer is removed in a further etch process. A silicon nitride removal process typically employs hot phosphoric acid. The etch selectivity of the anti-reflective coating layer to the layer of material, however, may be poor, particularly when the bottom anti-reflective coating layer is formed of silicon nitride and the gate electrode material is doped polysilicon. Pre-doped polysilicon, for example, is used in advanced field effect transistors to form the gate electrode to reduce undesired gate depletion. Doped polysilicon shows a higher etch rate compared to undoped polysilicon. The poor etch selectivity leads to an increased surface roughness and makes controlling of the critical dimension of the feature more difficult, which may affect the device performance or even lower the production yield of devices.
To explain in detail the use of bottom anti-reflective coating layers, according to a typical prior art process sequence, the process flow for forming a gate electrode of a MOS field effect transistor is described with reference to FIGS. 1a–1d, schematically depicting cross-sectional views of a partially formed field effect transistor.
FIG. 1a schematically depicts a semiconductor structure 1 comprising a silicon substrate 10 with shallow trench isolation (STI) regions 20, a gate insulation layer 30, a polysilicon layer 40 and a bottom anti-reflective coating layer 50 formed thereon. A typical process flow for forming the semiconductor structure 1 includes well-known isolation and deposition techniques and, thus, a description thereof will be omitted.
FIG. 1b depicts the semiconductor structure 1 after the formation of a gate electrode 41. The semiconductor structure 1 thus comprises the silicon substrate 10, the shallow trench isolation regions 20, a structured gate insulation layer 31, the gate electrode 41, a structured bottom anti-reflective coating layer 51 and a resist feature 61.
Forming the gate electrode 41 may include a photolithography process, wherein the bottom anti-reflective coating layer 50 reduces the reflection of light at the underlying inter-faces during the exposure of the photoresist. The bottom anti-reflective coating layer 50 may further act as an etch stop layer in the subsequent etch process. The etching of the resist layer and of the polysilicon layer 40 is typically performed in an anisotropic plasma etch process.
FIG. 1c depicts the semiconductor structure 1 after removal of the photoresist feature 61. The removal of the photoresist is typically performed by the use of an etch process.
FIG. 1d depicts the semiconductor structure 1 with the completed gate electrode 41. The structured bottom anti-reflective coating layer 51 is removed so that the semiconductor structure 1 comprises the silicon substrate 10, the shallow trench isolation regions 20, the gate insulation layer 31 and the gate electrode 41.
The silicon nitride bottom anti-reflective coating layer 51 is typically removed using hot phosphoric acid (H3PO4). Silicon nitride layers show relatively low etch rates in phosphoric acid and, hence, a poor etch selectivity to polysilicon. Due to the poor etch selectivity of silicon nitride compared to polysilicon, particularly to pre-doped polysilicon, long etch process times are required to reliably remove the bottom anti-reflective coating layer. The long process time causes undesired etching of the polysilicon device feature, i.e., the gate electrode 41. Thus, the surface roughness of the gate electrode 41 is increased, possibly to an extent that the shape thereof is altered. Moreover, controlling of the dimensions of the gate electrode 41 may be affected, and, consequently, these variations in shape and size may deteriorate the device performance.
Besides the drawback associated with the removal of the bottom anti-reflective coating layer 50, a second drawback in the fabrication of advanced MOS field effect transistor devices is emerging concerning the removal of disposable sidewall spacers. Disposable sidewall spacers are required to reduce the Miller (drain/gate) capacitance caused by the LDD/gate overlap generated in a typical prior art process as described in the following.
The use of sidewall spacers, according to a typical prior art process sequence (without disposable spacers), and the corresponding process flow for forming a MOS field effect transistor, is described with reference to FIGS. 2a–2f, wherein features identical to those illustrated in FIGS. 1a–1c are denoted by the same reference numerals.
FIG. 2a schematically depicts the semiconductor structure 1 during the lightly doped drain (LDD) implantation process 74. The semiconductor structure 1 comprises the silicon substrate 10, the shallow trench isolation regions 20, the patterned gate insulation layer 31, the gate electrode 41 and implanted LDD regions 71.
In the fabrication of MOS field effect transistor devices, source and drain regions of the transistor are formed after the formation of the gate electrode 41 in a self-aligning process. The shallow trench isolation regions 20 and the gate electrode 41 define active regions where the LDD implantation is effective. Depending on the type of ions, for example, phosphorus or boron, N-type or P-type MOS field effect transistors, respectively, may be formed. To provide the source and drain regions with the lightly doped drain (LDD) region 71, an according implantation of doping ions is performed.
FIG. 2b depicts the semiconductor structure 1 with a deposited silicon oxide or silicon nitride layer 80. The layer 80 may be blanket deposited using a well-known chemical vapor deposition (CVD) process. FIG. 2c depicts the semiconductor structure 1 after the formation of sidewall spacers 81.
After the formation of the LDD regions 71, the sidewall spacers 81 are formed to protect the extension regions of the LDD regions 71 and to define a region for the subsequent implantation process carried out to form heavily doped deep source/drain regions 72 of a source/drain 70 shown in FIG. 2d. The sidewall spacers 81 are formed in an anisotropic etch process, typically in a plasma etch process.
FIG. 2d depicts the semiconductor structure 1 during the deep source/drain implantation process 75. In addition to the semiconductor structure 1 of FIG. 2c, the implanted deep source/drain regions 72 are shown. The sidewall spacers 81 are employed to prevent the implantation of the ions into the extension regions of LDD regions 71 to generate the desired implantation profile.
FIG. 2e depicts the semiconductor structure 1 after performing the subsequent thermal annealing process. Thus, the LDD regions 71 comprise LDD/gate overlap portions 73. The annealing is required to incorporate the implanted ions into the semiconductor lattice, i.e., to activate the implanted ions, and to repair the damage of the crystal structure caused by the implanted ions. The annealing of the deep source/drain regions 72 and of the LDD regions 71 is typically carried out in a single annealing process. Annealing, however, also causes diffusion of the ions into the surrounding regions having a lower ion density. Due to the high diffusivity required for the deep source/drain annealing, the LDD ions diffuse also laterally under the gate electrode 41 and accordingly extend the LDD regions 71 under the gate electrode 41 and thus form the LDD/gate overlap portions 73. As a consequence, parasitic capacitances (drain/gate capacitance, known as Miller capacitance) are increased and the device performance may be further deteriorated.
FIG. 2f depicts the semiconductor structure 1 after the formation of silicide regions 91 in the source/drain regions 70 and on the gate electrode 41. The silicide regions 91 are formed in a conventional self-aligned silicide process. The silicide process may, for example, be performed by blanket depositing a metal layer and by a subsequent two-step thermal annealing process, wherein non-reacted excess metal is removed by an appropriate etch process after the first anneal step.
The undesired diffusion of the dopants of the LDD regions 71 under the gate insulation layer 31 can be prevented or at least reduced by varying the sequence of the process steps. An improved dopant concentration profile of the source/drain regions 70, with reduced LDD/gate overlap portions 73, may be achieved when the heavily doped deep source/drain regions 72 are implanted and annealed prior to the implantation of the LDD regions 71. Forming the LDD regions 71 after the annealing of the deep source/drain regions 72 permits the optimization of the required second (LDD) annealing process with respect to the LDD activation and lateral dopant diffusion. Varying the sequence of the process as mentioned, however, requires the removal of the sidewall spacers 81 after the formation of the deep source/drain regions 72. Typically, silicon nitride is employed as a material of the sidewall spacers 81. Due to the poor selectivity of the silicon nitride etch process to the adjacent doped silicon, the removal of the sidewall spacers 81 may lead to a device degradation caused by an incomplete removal of the silicon nitride spacer, thereby affecting subsequent processes, and/or by over-etching, thereby damaging silicon regions of the gate electrode 41 and the source/drain regions 70.
In view of the disadvantages of the conventional removal process of the bottom anti-reflective coating layer 50 and/or of the sidewall spacers 81, it is desirable to provide a method allowing the removal of device features without unduly sacrificing adjacent materials and/or negatively affecting subsequent process steps.